PEB20321 Datasheet, PDF (292/366 Pages) Siemens Semiconductor Group – Multichannel Network Interface Controller for HDLC MUNICH32X

PEB 20321
PEF 20321
Host Memory Organization
Interrupt Mask:
PCM Core:
31
30
29
28
27
26
25
24
FE2
SFE
IFC
CH
TE
RE
FIR
FIT
LBI:
31
30
29
28
27
26
25
24
FE2
0
0
0
TE
RE
FIR
FIT
These bits mask the bits in the interrupt information DWORD according to the table at
the end of Section 12.4 (interrupt bit fields definition).
If an event leads to an interrupt with several bits set (e.g. FI and ERR) masking only a
proper subset of them (e.g. ERR) will lead to an interrupt with the nonmasked bits set
(e.g., FI). If all bits of an event are masked, the interrupt is suppressed. The interrupt
mask is therefore bit specific and not event specific.
NITBS: New ITBS value; if this bit is set the individual Tx buffer size ITBS is valid and
a new buffer field of TB is assigned to the channel. In this process first the
occupied buffer locations of the channel are released and then according to
ITBS a new buffer area is allocated. If there is not enough buffer size in TB
(occupied by other channels) the process will be aborted and an action request
failure interrupt is generated. After aborting no buffer size is allocated to the
channel. For preventing action request failure enough buffer locations must be
available. This can be done by reducing the buffer size of the other channels.
To avoid transmission errors all channels to be newly configured must be
deactivated before processing.0
Note: ITBS has to be set to ‘0’ if NITBS = ‘0’.
NITBS should be set to ‘0’ in conjunction with a transmit abort channel command.
Note: For LBI channels ITBS has to be set to ‘10_H’, if NITBS is set to ‘1’.
Data Sheet
292
2001-02-14