PEB20321 Datasheet, PDF (205/366 Pages) Siemens Semiconductor Group – Multichannel Network Interface Controller for HDLC MUNICH32X

PEB 20321
PEF 20321
Reset and Initialization
Channel Status
Channel processing is deactivated. After reset, all buffers are empty and no buffer size
is allocated to the channels. The DMA controller state is set to the hold condition. The
descriptor and data pointers remain at a random value.
On reset, the bits RO and TO are set to ‘1’, whereas RA and TA are set to ‘0’ for all logical
channels. All time slots are connected to the logical channel 0 and the following
configuration is set:
Action Specification
LOC = LOOP = LOOPI = 0
Time Slot Assignment
fill/mask = 00_H, i.e., all bits masked/set to ‘1’
RTI, TTI = 0
channel number = 00_H
Channel Specification
MODE = 00, i.e. TMA
FA = 0
IFTF = 0
CRC = 0
INV = 0
TRV = 00,
RO = 1
RA = 0
TO = 1
TA = 0
TH = 0
Transmit Descriptor
FNUM = 00_H, i.e. shared flags in HDLC, only eight zero bits between sent frames for
TMB.
The E-, S-, X-bits are all set to zero internally by the reset. The receiver is set into the
ITF/IDLE state for all channels, i.e. it assumes that on the line there are ‘1’s as interframe
time-fill for HDLC.
Data Sheet
205
2001-02-14