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TLE7233G Datasheet, PDF (27/32 Pages) Infineon Technologies AG – SPI Driver for Enhanced Relay Control
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SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
9.5
Electrical Characteristics SPI
VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ. Max.
Input Characteristics (CS, SCLK, SI)
9.5.1
9.5.2
9.5.3
9.5.4
L level of pin
CS
SCLK
SI
H level of pin
CS
SCLK
SI
L-input pull-up current through CS
H-input pull-up current through CS
VCS(L)
VSCLK(L)
VSI(L)
VCS(H)
VSCLK(H)
VSI(H)
ICS(L)
ICS(H)
0
–
0.5*VDD –
5
17
3
15
9.5.5 L-input pull-down current through
3
12
pin
SCLK
SI
ISCLK(L)
ISI(L)
9.5.6 H-input pull-down current through
10
40
pin
SCLK
SI
ISCLK(H)
ISI(H)
Output Characteristics (SO)
0.2*
–
VDD
VDD
–
40
µA
VCS = 0 V
40
µA
1)
VCS = 2 V
80
µA
1)
VSCLK = 0.6 V
VSI = 0.6 V
80
µA
VSCLK = 5 V
VSI = 5 V
9.5.7
9.5.8
L level output voltage
H level output voltage
VSO(L)
0
–
VSO(H)
VDD-
–
0.5 V
0.4 V
VDD
ISO = -2 mA
ISO = 1.5 mA
9.5.9 Output tristate leakage current
ISO(OFF) -10
–
Timings
10
µA
VCS = VDD
9.5.10 Serial clock frequency
fSCLK
0
–
5
MHz –
9.5.11 Serial clock period
tSCLK(P) 200
–
–
ns –
9.5.12 Serial clock high time
tSCLK(H) 50
–
–
ns –
9.5.13 Serial clock low time
tSCLK(L)
50
–
–
ns –
9.5.14 Enable lead time (falling CS to
tCS(lead) 250
–
–
ns –
rising SCLK)
9.5.15 Enable lag time (falling SCLK to tCS(lag) 250
–
–
ns –
rising CS)
9.5.16 Transfer delay time (rising CS to tCS(td)
250
–
–
ns –
falling CS)
9.5.17 Data setup time (required time SI to tSI(su)
20
–
–
ns –
falling SCLK)
9.5.18 Data hold time (falling SCLK to SI) tSI(h)
20
–
–
ns –
Datasheet
27
Rev. 1.0, 2008-02-28
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