TLE4998S3C Datasheet, PDF (27/36 Pages) Infineon Technologies AG – Programmable Linear Hall Sensor

TLE4998S3C
Calibration
9.1
Calibration Data Memory
When the MEMLOCK bits are programmed (two redundant bits), the memory content is
frozen and may no longer be changed. Furthermore, the programming interface is locked
out and the chip remains in application mode only, preventing accidental programming
due to environmental influences.
Column Parity Bits
User-Calibration Bits
Pre-Calibration Bits
Figure 8 EEPROM Map
A matrix parity architecture allows automatic correction of any single-bit error. Each row
is protected by a row parity bit. The sum of bits set (including this bit) must be an odd
number (ODD PARITY). Each column is additionally protected by a column parity bit.
Each bit in the even positions (0, 2, etc.) of all lines must sum up to an even number
(EVEN PARITY), and each bit in the odd positions (1, 3, etc.) must have an odd sum
(ODD PARITY). The parity column must have an even sum (EVEN PARITY).
This system of different parity calculations also protects against many block errors (such
as erasing a full line or even the whole EEPROM).
When modifying the application bits (such as Gain, Offset, TC, etc.), the parity bits must
be updated. As for the column bits, the pre-calibration area must be read out and
considered for correct parity generation as well.
Note: A specific programming algorithm must be followed to ensure data retention.
A detailed separate programming specification is available on request.
Data Sheet
27
Rev 1.1, 2009-09