TLE7242-2G Datasheet, PDF (26/50 Pages) Infineon Technologies AG – 4 Channel Fixed Frequency Constant Current Control IC

TLE7242-2G
5.6.1 SPI Signal Description
Functional Description and Electrical Characteristics
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, T_j = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos. Parameter
5.6.1 T_LEAD
5.6.2 T_LAG
Symbol
t₁
Limit Values
Min. Typ. Max.
140 –
–
t₂
50
–
–
5.6.3
t₃
450 –
–
5.6.4
5.6.5
1/F_SCK Period of SCK
t₄
100 –
–
t₅
10
–
–
5.6.6
t₆
40
–
–
5.6.7
t₇
40
–
–
5.6.8
t₈
10
–
–
5.6.9 T_{SU_SI}
t₉
20
–
–
5.6.10 T_{HOLD_SI}
t₁₀
20
–
–
5.6.11 T_{SO_ENABLE}
t₁₁
–
–
110
5.6.12 T_VALID
t₁₂
–
–
80
5.6.13 T_{SO_DISABLE}
t₁₃
–
–
110
5.6.14 Number of clock pulses while CS_B
low
32
–
32
5.6.15 SO rise time
T_{SO_RISE} –
–
50
5.6.16 SO fall time
T_{SO_FALL} –
–
50
5.6.17 Input pin capacitance. CS_B, SI, C_in
–
–
20
and SCK
5.6.18 SO pin capacitance
C_so
–
–
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
Conditions
CS_B falling (0.8V)
to SCK rising (0.8V)
SCK falling (0.8V)
to CS_B rising
(0.8V)
CS_B rise (2.0V) to
CS_B fall (2.0V)
SCK rise to rise
SCK falling (0.8V)
to CS_B fall (2.0V)
SCK high time (rise
2.0V to fall 2.0V)
SCK low time (fall
0.8V to rise 0.8V)
CS_B rise (2.0V) to
SCK rise (0.8V)
SI setup time to
SCK rise (0.8V)
SI hold time after
SCK rise (2.0V)
CS_B fall (2.0V) to
SO Bit0 valid
SO data valid after
SCK rise (2.0V)
SO tristate after
CS_B rise (2.0V)
(20% to 80%)
(80% to 20%)
Tristate
Data Sheet
26
Rev. 1.0, 2008-07-09