HYS72D32300GBR-5-B Datasheet, PDF (24/48 Pages) Infineon Technologies AG – 184 - Pin Registered Double Data Rate SDRAM Modules

HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 12 AC Timing - Absolute Specifications –5/–6/–7 (cont’d)
Parameter
Symbol
–5
–6
DDR400B
DDR333
Min. Max. Min. Max.
Address and control input
t_IS
setup time
0.6 —
0.75 —
0.7 —
0.8 —
–7
DDR266A
Min. Max.
0.9 —
1.0 —
Unit Note/ Test
Condition ¹⁾
ns fast slew rate
3)4)5)6)10)
ns slow slew rate
3)4)5)6)10)
Address and control input hold t_IH
0.6
time
0.7
0.75 —
0.8 —
0.9 —
1.0 —
ns fast slew rate
3)4)5)6)10)
ns slow slew rate
3)4)5)6)10)
Read preamble
t_RPRE
Read postamble
t_RPST
Active to Precharge command t_RAS
Active to Active/Auto-refresh t_RC
command period
Auto-refresh to Active/Auto- t_RFC
refresh command period
Active to Read or Write delay t_RCD
Precharge command period t_RP
Active to Autoprecharge delay t_RAP
Active bank A to Active bank B t_RRD
command
Write recovery time
t_WR
Auto precharge write recovery t_DAL
+ precharge time
Internal write to read
t_WTR
command delay
Exit self-refresh to non-read t_XSNR
command
Exit self-refresh to read
command
t_XSRD
Average Periodic Refresh
t_REFI
Interval
0.9 1.1
0.9 1.1
0.90 1.1
t ^2)3)4)5)
CK
0.4 0.6
0.4 0.6
0.4 0.6
t ^2)3)4)5)
CK
40
70E+3 42
70E+3 45
70E+3 ns ^2)3)4)5)
55
60 —
65 —
ns ^2)3)4)5)
65
72 —
75 —
ns ^2)3)4)5)
15 —
15 —
t_RCD or
t_RASmin
10 —
18 —
18 —
t_RCD or
t_RASmin
12 —
20 —
20 —
t_RCDor —
t_RASmin
15 —
ns ^2)3)4)5)
ns ^2)3)4)5)
ns ^2)3)4)5)
ns ^2)3)4)5)
15 —
—
2
—
75 —
15 —
—
1
—
75 —
15 —
—
1
—
75 —
ns ^2)3)4)5)
t ^2)3)4)5)11)
CK
t ^2)3)4)5)
CK
ns ^2)3)4)5)
200 —
—
7.8
200 —
— 7.8
200 —
— 7.8
t ^2)3)4)5)
CK
µs ^2)3)4)5)12)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
24
Rev. 1.1, 2004-04
10102003-01E2-HPA8