TLE7232GS Datasheet, PDF (23/32 Pages) Infineon Technologies AG – SPI Driver for Enhanced Relay Control

SPI Driver for Enhanced Relay Control
SPIDER - TLE7232GS
Block Description and Electrical Characteristics
5.4
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
SO
SI
CS
SCLK
time
MSB 14 13 12 11 10
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MSB 14 13 12 11 10
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SPI.emf
Figure 12 Serial Peripheral Interface
The SPI protocol is described in Section 5.4.5. It is reset to the default values after power-on reset or a low signal
at pin RST.
5.4.1 SPI Signal Description
CS - Chip Select: The system microcontroller selects the SPIDER - TLE7232GS by means of the CS pin.
Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK
and SI pins are ignored and SO is forced into a high impedance state.
CS High to Low Transition:
• The diagnosis information is transferred into the shift register.
CS Low to High Transition:
• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected.
• Data from shift register is transferred into the input matrix register.
• The diagnosis flags are cleared.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 16 bit input data consist of two parts (control and data). Please refer to
Section 5.4.5 for further information.
SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state
until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please
refer to Section 5.4.5 for further information. The high state output voltage depends on the voltage at pin V_SO.
Data Sheet
23
Rev. 1.0, 2007-12-18