TLE5012 Datasheet, PDF (23/57 Pages) Infineon Technologies AG – GMR-Based Angular Sensor for Rotor Position Sensing

TLE5012
Specification
3.4.6 Clock Supply (CLK Timing Definition)
If the external clock supply is selected, the clock signal input ’CLK’ must fulfill certain requirements which are
described in the following:
• The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike filtered.
• The duty cycle factor should be 0.5 but can deviate to the values limited by t_{CLKh(f_min)} and t_{CLKl(f_min)}.
• The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
generated automatically.
tCLKh
tCLK
tCLKl
Figure 13 External CLK Timing Definition
V_H
V_L
t
Table 9 CLK Timing Specification
Parameter
Symbol
Values
Unit
Min. Typ. Max.
Input Frequency
f_CLK
3.8 4.0 4.2
MHz
CLK Duty Cycle¹⁾²⁾
CLK_DUTY 30
50
70
%
CLK Rise Time
t_CLKr
-
-
30
ns
CLK Fall Time
t_CLKf
-
-
30
ns
Digital Clock
f_DIG
22.8 24 25.2
MHz
Internal Oscillator Frequency
f_CLK
3.8 4.0 4.2
MHz
1) Minimum Duty Cycle Factor: t_{CLKh(f_min)} / t_{CLK(f_min)} with t_{CLK(f_min)}= 1 / f_{CLK(f_min)}
2) Maximum Duty Cycle Factor: t_{CLKh(f_max)} / t_{CLK(f_min)} with t_{CLKh(f_max)}= t_{CLK(f_min)} - t_CLKl(min)
Note / Test Condition
from V_L to V_H
from V_H to V_L
Target Data Sheet
23
V 0.46, 2009-09