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TLE7184F_15 Datasheet, PDF (22/38 Pages) Infineon Technologies AG – System IC for B6 motor drives
TLE7184F
Interface, VDH Switch and INH Digital Output
8.2
VDHS Switch
The System IC has an integrated switch connecting the VDH pin to the VDHS pin. This allows to place an external
voltage divider for VDH voltage monitoring at the VDHS pin and to disconnect this voltage divider from VDH during
sleep mode to assure low current consumption. The VDHS switch is only deactivated when the VDD regulator is
switched off.
8.3
Digital Output INHD
The System IC provides a digital output INHD showing the logic state of INH (e.g. KL15) after a complete wake-
up of the driver (approx. 1ms). The input levels of INH for the INHD output are defined separately from the levels
for wake-up. Voltage levels for INH wake-up function please see Chapter 9.4 section Wake-up and go-to-sleep.
The output stage consists of an integrated low side switch with a pull-up resistor to VDD.
8.4
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 6.0 to 20V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
Interface - static parameters
8.4.1 IFMA input voltage high level
VIMHL
59
–
–
%
of VVS; IC not in
(for IFµC high)
Sleep Mode
8.4.2 IFMA input voltage low level
(for IFµC low)
VIMLL
–
–
46
%
of VVS; IC not in
Sleep Mode;
8.4.3 IFMA input hysteresis
(for IFµC)
VIMhy
0.5
–
9
%
of VVS; IC not in
Sleep Mode
8.4.4 IFMA wake up voltage high level VIMWH 2
–
4
V
valid in Sleep Mode
= VS-VIFMA
8.4.5 IFMA low time to guarantee wake- tIFlow
100 –
–
µs
VVS=7...20V
up
8.4.6
8.4.7
IFMA internal pull-up resistor to VS RIMu
IFMA internal pull-down resistor to RIMd
GND
210 340 495 kΩ –
420 700 980 kΩ not active in Sleep
Mode
8.4.8 IFMA input current related to VS IIFMA/VVS
VIFMA = 59% of VVS
-2.0 –
VIFMA = 46% of VVS
-3.0 –
8.4.9 IFµC output low voltage
VIuLL
–
–
8.4.10 IFµC internal pull-up resistor to VDD RIu
8.5
–
Interface - dynamic parameters
+2.0
+1.0
0.5
23
µA/V –
V
no external load
kΩ –
8.4.11 IFµC duty cycle
dIu
0
–
100 %
–
8.4.12 Propagation time rising edge IFµC tPRE
–
–
6
µs Including rise time
to 80% of VVDD;
Cload=100pF
8.4.13 Propagation time falling edge IFµC tPFE
–
–
5
µs Including fall time to
20% of VVDD;
Cload=100pF
Data Sheet
22
Rev. 1.1, 2011-04-08