HYS64T64020KM Datasheet, PDF (21/31 Pages) Infineon Technologies AG – Double-Data-Rate-Two SDRAM Micro-DIMM

HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Electrical Characteristics & AC Timings
5
Electrical Characteristics & AC Timings
Table 16 AC Timing - Absolute Specifications −5/−3.7¹⁾
Parameter
Symbol −3.7
−5
Unit Notes
PC2-4200M
PC2-3200M
Min.
Max.
Min.
Max.
DQ output access time from CK/CK t_AC
CAS A to CAS B Command Period t_CCD
CK, CK high-level width
t_CH
Clock cycle time
t_CK3
t_CK4
CKE minimum high and low pulse t_CKE
width
-500
2
0.45
5000
3750
3
+500
—
0.55
8000
8000
—
−600
2
0.45
5000
5000
3
+600
—
0.55
8000
8000
—
ps
t_CK
t_CK
ps ²⁾
ps ³⁾
t_CK
CK, CK low-level width
t_CL
0.45
0.55
0.45
0.55
t_CK
Auto precharge write recovery +
t_DAL
WR + t_RP —
WR + t_RP —
t_CK
precharge time
Minimum time clocks remain ON
t_DELAY t_IS + t_CK + t_IH —
t_IS + t_CK+ t_IH —
ns
after CKE asynchronously drops low
DQ and DM input hold time
t_DH
225
—
275
—
ps
DQ and DM input pulse width (each t_DIPW 0.35
—
0.35
—
t_CK
input)
DQS output access time from CK/CK t_DQSCK
DQS input low (high) pulse width
(write cycle)
t_DQSL,H
−450
0.35
+450
—
−500
0.35
+500
ps
—
t_CK
DQS-DQ skew (for DQS &
associated DQ signals)
t_DQSQ
—
300
—
350
ps
Write command to 1st DQS latching t_DQSS
transition
WL - 0.25 WL + 0.25 WL − 0.25 WL + 0.25 t_CK
DQ and DM input setup time
t_DS
100
—
150
—
ps
DQS falling edge hold time from CLK t_DSH
0.2
(write cycle)
—
0.2
—
t_CK
DQS falling edge to CLK setup time t_DSS
0.2
(write cycle)
—
0.2
—
t_CK
Clock Half Period
t_HP
Data-out high-impedance time from t_HZ
CK/CK
min. (t_CL, t_CH)
min. (t_CL, t_CH)
t_CK
—
t_ACmax
—
t_ACmax
ps
Address and control input hold time t_IH
375
—
475
—
ps
Control and Addr. input pulse width t_IPW
0.6
(each input)
—
0.6
—
t_CK
Address and control input setup time t_IS
250
—
350
—
ps
DQ low-impedance from CK / CK
t_LZ(DQ)
2×t_ACmin
t_ACmax
2×t_ACmin
t_ACmax
ps
DQS low-impedance from CK / CK t_LZ(DQS) t_ACmin
t_ACmax
t_ACmin
t_ACmax
ps
Mode register set command cycle t_MRD
2
time
—
2
—
t_CK
OCD drive mode output delay
t_OIT
0
12
0
12
ns
Data Sheet
21
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X