HYS64D32020GDL5C Datasheet, PDF (20/30 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Modules

HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 12 AC Timing - Absolute Specifications for DDR400B and DDR333 (cont’d)
Parameter
Symbol
–5
–6
Unit
DDR400B
DDR333
Min. Max. Min. Max.
Address and control input hold t_IH
time
0.6 —
0.75 —
ns
0.7 —
0.8 —
ns
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-
refresh command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
t_RPRE
t_RPST
t_RAS
t_RC
t_RFC
t_RCD
t_RP
t_RAP
0.9 1.1
0.9 1.1
t_CK
0.40 0.60 0.40 0.60
t_CK
40 70E+3 42 70E+3 ns
55 —
60 —
ns
65 —
72 —
ns
15 —
18 —
ns
15 —
18 —
ns
t_RCD or t_RASmin t_RCD or t_RASmin ns
Note/ Test
Condition ¹⁾
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read
command
Average Periodic Refresh
Interval
t_RRD
t_WR
t_DAL
t_WTR
t_XSNR
t_XSRD
t_REFI
10 —
12 —
ns
15 —
15 —
ns
—
—
—
—
t_CK
2
—
1
—
t_CK
75 —
75 —
ns
200 —
200 —
t_CK
— 7.8
— 7.8
µs
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Data Sheet
20
Rev. 1.0, 2004-03