ICE3AR1580VJZ Datasheet, PDF (18/43 Pages) Infineon Technologies AG – Of f -Line SMPS Cur rent Mode Cont rol ler wi th integrated 800V

CoolSET™ F3R80
ICE3AR1580VJZ
Functional Description
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the
switch on slope when exceeding the integrated CoolMOS™ threshold. This is achieved by a slope control of the
rising edge at the driver’s output (Figure 17) and adding a 50Ω gate turn on resistor (Figure 15). Thus the leading
switch on spike is minimized.
(internal)
V_Gate
4.6V
Figure 17: Gate Rising Slope
typ. t = 160ns
t
Furthermore the driver circuit is designed to eliminate cross conduction of the output stage.
During power up, when VCC is below the undervoltage lockout threshold V_VCCoff, the output of the Gate Driver is set
to low in order to disable power transfer to the secondary side.
3.6
Current Limiting
PWM Latch
FF1
Propagation-Delay
Compensation
Current Limiting
PWM-OP
&
G10
Active Burst
Mode
VFB_burst
C5
Vcsth
C10
LEB
220ns
S4
LEB
C12
180ns
VCSth_burst
Propagation-Delay
Compensation-Burst
or
G13
10k
1pF
D1
FBB
CS
Figure 18: Current Limiting Block
There is a cycle by cycle peak current limiting operation realized by the Current-Limit comparator C10. The source
current of the integrated CoolMOS™ is sensed via an external sense resistor R_Sense. By means of R_Sense the source
current is transformed to a sense voltage V_Sense which is fed into the pin CS. If the voltage V_Sense exceeds the internal
threshold voltage V_csth, the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to support the immediate shut down of the integrated CoolMOS™
with very short propagation delay. Thus the influence of the AC input voltage on the maximum output power can
be reduced to minimal. This compensation applies to both the peak load and burst mode.
In order to prevent the current limit from distortions caused by leading edge spikes, a Leading Edge Blanking
(LEB) is integrated in the current sense path for the comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. When it is activated,
the current limiting is reduced to V_{csth_burst}. This voltage level determines the maximum power level in Active
Burst Mode.
Data Sheet
18
V2.0, 2014-01-20