ICE3AR1580VJZ Datasheet, PDF (17/43 Pages) Infineon Technologies AG – Of f -Line SMPS Cur rent Mode Cont rol ler wi th integrated 800V

3.5
PWM Section
0.75
Oscillator
Duty Cycle
max
Clock
Frequency
Jitter
PWM Section
CoolSET™ F3R80
ICE3AR1580VJZ
Functional Description
Soft Start
Block
Soft Start
Comparator
PWM
Comparator
Current
Limiting
Figure 15: PWM Section Block
FF1
1
S
Gate Driver
G8
RQ
&
G9
CoolMOS^®
Gate
3.5.1 Oscillator
The oscillator generates a fixed frequency of 100kHz with frequency jittering of ±4% (which is ±4KHz) at a
jittering period of 4ms.
A capacitor, a current source and current sink which determine the frequency are integrated. The charging and
discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a very accurate
switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle
limitation of D_max=0.75.
Once the Soft Start period is over and when the IC goes into normal operating mode, the switching frequency of the
clock is varied by the control signal from the Soft Start block. Then the switching frequency is varied in range of
100kHz ± 4KHz at period of 4ms.
3.5.2 PWM-Latch FF1
The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the integrated
CoolMOS™. After the PWM-Latch is set, it is reset by the PWM comparator, the Soft Start comparator or the
Current -Limit comparator. When it is in reset mode, the output of the driver is shut down immediately.
3.5.3 Gate Driver
VCC
PWM-Latch
1
50
Gate
CoolMOS^®
Figure 16: Gate Driver
Gate Driver
Data Sheet
17
V2.0, 2014-01-20