TLE8104E Datasheet, PDF (17/27 Pages) Infineon Technologies AG – Smart Quad Channel Powertrain Switch

TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
Electrical Characteristics: SPI Interface (cont’d)
V_S = 4.5 V to 5.5 V, T_j = -40 °C to +150 °C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
5.5.6
Serial Clock Period (1/f_sclk)
(depending on SO load)
t_pSCLK
200
–
–
ns
–
5.5.7 Serial Clock High Time
t_SCLK(H) 50
–
–
ns
–
5.5.8 Serial Clock Low Time
t_SCLK(L)
50
–
–
ns
–
5.5.9 Enable Lead Time (falling edge of t_lead
250 –
–
ns
–
CS to rising edge of SCLK)
5.5.10 Enable Lag Time (falling edge of t_lag
250 –
–
ns
–
SCLK to rising edge of CS)
5.5.11 Data Setup Time (required time SI t_SU
20
–
–
ns
–
to falling of SCLK)
5.5.12 Data Hold Time (falling edge of t_H
SCLK to SI)
20
–
–
ns
–
5.5.13
5.5.14
Disable Time¹⁾
t_DIS
Transfer Delay Time²⁾ (CS high time t_dt
between two accesses)
–
–
200 –
150 ns
–
–
ns
–
5.5.15 Data Valid Time¹⁾
t_valid
–
110 160 ns
120 170
150 200
C_L = 50 pF
C_L = 100 pF
C_L = 220 pF
5.5.16 Input Low Voltage
V_SI(L),
-0.3
–
V_CS(L),
V_SCLK(L)
1.0
V
–
5.5.17 Input High Voltage
5.5.18 Input Voltage Hysteresis¹⁾
V_SI(H),
2.0
V_CS(H),
V_SCLK(H)
V_SI(Hys), 50
V_CS(Hys),
V_SCLK(Hys)
–
V_S+0.3 V
–
100 200 mV –
5.5.19 SO Tri-state leakage current
I_SOlkg
-10
1) Not subject to production test, specified by design.
10
µA CS = 1,
0 V ≤ V_SO ≤ V_S
2) This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has
to be extended to the maximum fault delay time t_d(fault)max = 200 µs.
Data Sheet
17
V1.4, 2010-04-26