TLE8104E Datasheet, PDF (15/27 Pages) Infineon Technologies AG – Smart Quad Channel Powertrain Switch

TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.5
SPI Interface
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
SO
SI
CS
SCLK
time
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
Figure 10 Serial Peripheral Interface
The SPI protocol is described in Section 6. All registers are reset to default values after power-on reset or if the
chip is programmed via SPI to enter sleep mode.
5.5.1 SPI Signal Description
CS - Chip Select: The system micro controller selects the TLE8104E by means of the CS pin. Whenever the pin
is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are
ignored and SO is forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
CS Low to High transition:
• Command decoding is only done after the falling edge of CS and a exact multiple (1, 2, 3, …) of eight SCLK
signals have been detected.
• Data from shift register is transferred into the input matrix register.
• The diagnosis flags are cleared.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 6
for further information.
SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance
state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Section 6 for further information.
Data Sheet
15
V1.4, 2010-04-26