XC164SM_07 Datasheet, PDF (16/67 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164SM
Derivatives
Functional Description
3
Functional Description
The architecture of the XC164SM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164SM.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164SM.
PSRAM
2 Kbytes
ProgMem
Fla sh
32/64/128 Kbytes
OCDS
Debug Support
Osc / PLL RTC WDT
XTAL _{Clock Generation}
DPRAM
2 Kbytes
CPU
C166SV2-Core
DSRAM
0/2/4 Kbytes
Interrupt & PEC
Interrupt Bus
Peripheral Data Bus
ADC
8/10-Bit
14
C hannels
GPT
T2
T3
ASC0 ASC1 SSC0 SSC1
(U SAR T) (U SAR T) (SPI) (SPI)
T4
T5
T6
BR Gen BR Gen BR Gen BR Gen
Port 9
Port 5
Port 3
6
14
13
CC2
T7
T8
CC6
T12
T13
POR T1
14
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Figure 3 Block Diagram
Data Sheet
14
V1.2, 2007-03