XC164SM_07 Datasheet, PDF (13/67 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164SM
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Sym- Pin Input Function
bol
Num. Outp.
Port 3 28-39, IO
42
P3.1 28
O
I/O
I
I
P3.2 29
I
I
P3.3 30
O
O
P3.4 31
I
I
P3.5 32
I
O
O
P3.6 33
I
P3.7 34
I
I
P3.8 35
I/O
P3.9 36
I/O
P3.10 37
O
I
P3.11 38
I/O
I
P3.13 39
I/O
I
P3.15 42
O
O
Port 3 is a 13-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance state)
or output (configurable as push/pull or open drain driver). The
input threshold of Port 3 is selectable (standard or
special).The following Port 3 pins also serve for alternate
functions:
T6OUT: [GPT2] Timer T6 Toggle Latch Output,
RxD1: [ASC1] Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN: [Fast External Interrupt 1] Input (alternate pin A),
TCK: [Debug System] JTAG Clock Input
CAPIN: [GPT2] Register CAPREL Capture Input,
TDI: [Debug System] JTAG Data In
T3OUT: [GPT1] Timer T3 Toggle Latch Output,
TDO: [Debug System] JTAG Data Out
T3EUD: [GPT1] Timer T3 External Up/Down Control Input,
TMS: [Debug System] JTAG Test Mode Selection
T4IN: [GPT1] Timer T4 Count/Gate/Reload/Capture Inp.
TxD1: [ASC0] Clock/Data Output (Async./Sync.),
BRKOUT: [Debug System] Break Out
T3IN: [GPT1] Timer T3 Count/Gate Input
T2IN: [GPT1] Timer T2 Count/Gate/Reload/Capture Inp.
BRKIN: [Debug System] Break In
MRST0: [SSC0] Master-Receive/Slave-Transmit In/Out.
MTSR0: [SSC0] Master-Transmit/Slave-Receive Out/In.
TxD0: [ASC0] Clock/Data Output (Async./Sync.),
EX2IN: [Fast External Interrupt 2] Input (alternate pin B)
RxD0: [ASC0] Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN: [Fast External Interrupt 2] Input (alternate pin A)
SCLK0: [SSC0] Master Clock Output / Slave Clock Input.,
EX3IN: [Fast External Interrupt 3] Input (alternate pin A)
CLKOUT: System Clock Output (= CPU Clock),
FOUT: Programmable Frequency Output
Data Sheet
11
V1.2, 2007-03