ICE3AR0680JZ Datasheet, PDF (16/34 Pages) Infineon Technologies AG – Of f -Line SMPS Cur rent Mode Cont rol ler wi th integrated 800V

CoolSET^®-F3R80
ICE3AR0680JZ
Functional Description
C_FB
>=6.8nF
(5%,X7R)
1nF~2.2nF
(1%,COG)
220pF~470pF
(1%,COG)
<=100pF
(1%,COG)
Entry level
% of
P_{in_max}
10%
V_{FB_burst}
1.60V
Exit level
% of
P_{in_max}
20%
V_{csth_burst}
0.45V
6.67% 1.42V 13.3% 0.37V
4.38% 1.27V 9.6% 0.31V
0%
never
0%
always
The selection is at the 1st 1ms of the UVLO “ON” (Vcc
> 17V) during the 1st start up but it does not detect in
the subsequent re-start due to auto-restart protection.
In case there is protection triggered such as auto
restart enable or brownout before starts up, the
detection will be held until the protection is removed.
When the Vcc reaches the UVLO “ON” in the 1st start
up, the capacitor C_FB at FBB pin is charged by a 5V
voltage source through the R_FB resistor. When the
voltage at FBB pin hits 4.5V, the FF4 will be set, the
switch S9 is turned “ON” and the counter will increase
by 1. Then the C_FB is discharged through a 500W
resistor. After reaching 0.5V, the FF4 is reset and the
switch S9 is turned “OFF”. Then the C_FB capacitor is
charged by the 5V voltage source again until it reaches
4.5V. The process repeats until the end of 1ms. Then
the detection is ended. After that, the total number of
count in the counter is compared and the V_FB-burst and
the V_{cs_burst} are selected accordingly (Figure 25).
falls below V_{FB_burst}, it starts to count. When the counter
reaches 20ms and FBB signal is still below V_{FB_burst}, the
system enters the Active Burst Mode. This time window
prevents a sudden entering into the Active Burst Mode
due to large load jumps.
After entering Active Burst Mode, a burst flag is set and
the internal bias is switched off in order to reduce the
current consumption of the IC to about 620uA.
It needs the application to enforce the VCC voltage
above the Undervoltage Lockout level of 10.5V such
that the Startup Cell will not be switched on
accidentally. Or otherwise the power loss will increase
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the
application. The lowest VCC level is reached at no load
condition.
3.7.2.3 Working in Active Burst Mode
After entering the Active Burst Mode, the FBB voltage
rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors
the FBB signal. If the voltage level is larger than 3.5V,
the internal circuit will be activated; the Internal Bias
circuit resumes and starts to provide switching pulse. In
Active Burst Mode the gate G10 is released and the
current limit is reduced to Vcsth_burst (Figure 2 and
24). In one hand, it can reduce the conduction loss and
the other hand, it can reduce the audible noise. If the
load at VOUT is still kept unchanged, the FBB signal
will drop to 3.2V. At this level the C6b deactivates the
internal circuit again by switching off the Internal Bias.
The gate G11 is active again as the burst flag is set
after entering Active Burst Mode. In Active Burst Mode,
the FBB voltage is changing like a saw tooth between
3.2V and 3.5V (Figure 26).
5V
VFB_burst
VCSth_burst
FBB
C_FB
R_FB
4.5V _C19
500 ^{0.5V C20}
1ms
UVLO during
1^st startup
timer
S9
Comparator _counter
logic
UVLO
SQ
FF4
R
3.7.2.4 Leaving Active Burst Mode
The FBB voltage will increase immediately if there is a
high load jump. This is observed by the comparator
C13 (Figure 24). Since the current limit is reduced to
31%~45% of the maximum current during active burst
mode, it needs a certain load jump to rise the FBB
signal to exceed 4.0V. At that time the comparator C5
resets the Active Burst Mode control which in turn
blocks the comparator C12 by the gate G10. The
maximum current can then be resumed to stabilize
V_OUT.
Control Unit
Figure 25 Entry burst mode detection
3.7.2.2 Entering Active Burst Mode
The FBB signal is kept monitoring by the comparator
C5 (Figure 24). During normal operation, the internal
blanking time counter is reset to 0. When FBB signal
Version 2.1a
16
11 Jan 2012