ICE3AR0680JZ Datasheet, PDF (12/34 Pages) Infineon Technologies AG – Of f -Line SMPS Cur rent Mode Cont rol ler wi th integrated 800V

CoolSET^®-F3R80
ICE3AR0680JZ
Functional Description
The Start-Up time t_Start-Up before the converter output
voltage V_OUT is settled, must be shorter than the Soft-
Start Phase t_Soft-Start (Figure 13). By means of Soft-Start
there is an effective minimization of current and voltage
stresses on the integrated CoolMOS^®, the clamp circuit
and the output rectifier and it helps to prevent
saturation of the transformer during Start-Up.
3.5
PWM Section
0.75
Oscillator
Duty Cycle
max
PWM Section
3.5.2
PWM-Latch FF1
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the
integrated CoolMOS^®. After the PWM-Latch is set, it is
reset by the PWM comparator, the Soft Start
comparator or the Current -Limit comparator. When it is
in reset mode, the output of the driver is shut down
immediately.
3.5.3
Gate Driver
VCC
PWM-Latch
1
Clock
Frequency
Jitter
Soft Start
Block
Soft Start
Comparator
PWM
Comparator
Current
Limiting
FF1
1
S
Gate Driver
G8
RQ
&
G9
CoolMOS^®
Gate
Figure 14 PWM Section Block
50
Gate
CoolMOS^®
Gate Driver
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the integrated
CoolMOS^® threshold. This is achieved by a slope
control of the rising edge at the driver’s output (Figure
16) and adding a 50W gate turn on resistor (Figure 15).
Thus the leading switch on spike is minimized.
3.5.1
Oscillator
The oscillator generates a fixed frequency of 100KHz
with frequency jittering of ±4% (which is ±4KHz) at a
jittering period of 4ms.
A capacitor, a current source and current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D_max=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 100KHz ± 4KHz at period of 4ms.
(internal)
V_Gate
typ. t = 160ns
4.6V
t
Figure 16 Gate Rising Slope
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
Version 2.1a
12
11 Jan 2012