TLE9262-3QX Datasheet, PDF (145/197 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9262-3QX
Serial Peripheral Interface
before entering SBC Stop Mode. Please refer to Chapter 5.4.4 for detailed information on the Selective Wake
mode changes.
6. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0
1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.
BUS_CTRL_2
Bus Control (Address 000 0101_B)
POR / Soft Reset Value: 0000 0000_B; Restart Value: 00x0 0000_B
7
6
5
4
3
2
1
0
Reserved
r
Reserved I_PEAK_TH Reserved
r
rw
r
Reserved
r
Reserved Reserved
r
r
r
Reserved
r
Field
Bits
Reserved 7:6
I_PEAK_TH 5
Reserved 4:0
Type
r
rw
r
Description
Reserved, always reads as 0
VCC1 Active Peak Threshold Selection
0_B , low VCC1 active peak threshold selected (ICC1,peak_1)
1_B , higher VCC1 active peak threshold selected (ICC1,peak_2)
Reserved, always reads as 0
Notes
1. The bit I_PEAK_TH can be modified in SBC Init and Normal Mode. In SBC Stop Mode this bit is Read only but
SPI_FAIL will not be set when trying to modify the bit in SBC STOP Mode and no INT is triggered in case INT_
GLOBAL is set.
2. see Figure 31 for detailed state changes of CAN Transceiver for different SBC modes
3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers BUS_CTRL_1, BUS_CTRL_2 and WK_CTRL_2 are reset to following values (=wake
sources) ‘xxx0 1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.
Data Sheet
145
Rev. 1.1, 2014-09-26