HYS64V16300GU Datasheet, PDF (14/20 Pages) Infineon Technologies AG – 3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules

HYS 64/72V16300/32220GU
SDRAM-Modules
SPD-Table for PC133-333 Modules:
Byte#
Description
SPD Entry
Hex
Value
0 Number of SPD bytes
16Mx64 16Mx72 32Mx64 32Mx72
-7.5
-7.5
-7.5
-7.5
128
80
1 Total bytes in Serial PD
256
08
2 Memory Type
SDRAM
04
3 Number of Row Addresses
12
0C
(without BS bits)
4 Number of Column Addres-
10
0A
ses
5 Number of DIMM Banks
1/2
01
02
6 Module Data Width
7 Module Data Width (cont’d)
64 / 72
0
40
48
40
48
00
8 Module Interface Levels
LVTTL
01
9 SDRAM Cycle Time at CL=3
7.5 ns
75
10 SDRAM Access time from
5.4 ns
54
Clock at CL=3
11 Dimm Config
none / ECC
00
02
00
02
12 Refresh Rate/Type
Self-Refresh,
80
15.6 µs
13 SDRAM width,Primary
14 Error Checking SDRAM data
width
x8
n/a / x8
08
00
08
00
08
15 Minimum clock delay for
t_ccd = 1 CLK
01
back-to-back random column
address
16 Burst Length supported
1, 2, 4 & 8
0F
17 Number of SDRAM banks
4
04
18 Supported CAS Latencies CAS latency = 2
06
&3
19 CS Latencies
CS latency = 0
01
20 WE Latencies
Write latency = 0
01
21 SDRAM DIMM module
non buffered/non
00
attributes
reg.
22 SDRAM Device Attributes
Vcc tol +/- 10%
0E
:General
23 Min. Clock Cycle Time at
10.0 ns
A0
CAS Latency = 2
24 Max. data access time from
6.0 ns
60
Clock for CL=2
25 Minimum Clock Cycle Time not supported
FF
at CL = 1
26 Maximum Data Access Time not supported
FF
from Clock at CL=1
27 Minimum Row Precharge
20 ns
14
Time
28 Minimum Row Active to Row
15 ns
0F
Active delay tRRD
INFINEON Technologies
14
9.01