ICE3BR2565JF Datasheet, PDF (13/36 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS and Startup cell (frequency jitter Mode) in FullPak

3.5.3
Gate Driver
VCC
CoolSET^®-F3R
ICE3BR2565JF
Functional Description
3.6
Current Limiting
PWM Latch
FF1
Current Limiting
PWM-Latch
1
Gate
CoolMOS^®
Gate Driver
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the internal
CoolMOS^® threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 9).
Propagation-Delay
Compensation
V_csth
C10
Leading
Edge
PWM-OP
Blanking
220ns
&
G10
C12
0.26V
Active Burst
Mode
10k
1pF
D1
(internal)
V_Gate
ca. t = 130ns
5V
t
Figure 16 Gate Rising Slope
Thus the leading switch on spike is minimized.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout threshold V_VCCoff, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
CS
Figure 17 Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS^® is sensed
via an external sense resistor R_Sense. By means of
R_Sense the source current is transformed to a sense
voltage V_Sense which is fed into the pin CS. If the voltage
V_Sense exceeds the internal threshold voltage V_csth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
CoolMOS^® with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking is integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. When it is
activated, the current limiting is reduced to 0.26V. This
voltage level determines the maximum power level in
Active Burst Mode.
Version 2.0
13
11 Sep 2008