ICE3BR2565JF Datasheet, PDF (10/36 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS and Startup cell (frequency jitter Mode) in FullPak

Soft-Start Comparator
PWM Comparator
FB
Oscillator
C8
PWM-Latch
V_OSC
T₂
time delay
circuit (156ns)
Gate Driver
0.68V
10kΩ
R₁
X3.3
V_{1 PWM OP}
Voltage Ramp
CoolSET^®-F3R
ICE3BR2565JF
Functional Description
3.3.1 PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
R_Sense connected to pin CS. R_Sense converts the source
current into a sense voltage. The sense voltage is
amplified with a gain of 3.3 by PWM OP. The output of
the PWM-OP is connected to the voltage source V₁.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
3.3.2 PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOS^® with the feedback
signal V_FB (see Figure 8). V_FB is created by an external
optocoupler or external transistor in combination with
the internal pull-up resistor R_FB and provides the load
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS^®
exceeds the signal V_FB the PWM-Comparator switches
off the Gate Driver.
Figure 6 Improved Current Mode
V_OSC
max.
Duty Cycle
Voltage Ramp
0.68V
FB
Gate Driver
156ns time delay
5V
R_FB
Soft-Start Comparator
FB
PWM-Latch
C8
PWM Comparator
t
0.68V
Optocoupler
PWM OP
CS
X3.3
t
Improved
Current Mode
Figure 7 Light Load Conditions
Figure 8 PWM Controlling
t
Version 2.0
10
11 Sep 2008