XC2261N Datasheet, PDF (12/130 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2261N, XC2263N, XC2264N, XC2265N, XC2268N
XC2000 Family / Value Line
Summary of Features
Table 5
Interface Channel Association
Total Number
Available Channels / Message Objects
6 CAN nodes
CAN0, CAN1, CAN2,CAN3, CAN4, CAN5
256 message objects
2 serial channels
U0C0, U0C1
4 serial channels
U0C0, U0C1, U1C0, U1C1
6 serial channels
U0C0, U0C1, U1C0, U1C1, U2C0, U2C1
The XC226xN types are offered with several SRAM memory sizes. Figure 1 shows the
allocation rules for PSRAM and DSRAM. Note that the rules differ:
• PSRAM allocation starts from the lower address
• DSRAM allocation starts from the higher address
For example 8 Kbytes of PSRAM will be allocated at E0’0000h-E0’1FFFh and 8 Kbytes
of DSRAM will be at 00’C000h-00’DFFFh.
E7'FFFFh
(EF'FFFFh)
Reserved for
PSRAM
00'DFFFh
Available
DSRAM
Available
PSRAM
E0'0000h
(E8'0000h)
Figure 1 SRAM Allocation
00'8000h
Reserved for
DSRAM
MC_XC_SRAM_ALLOCATION
Data Sheet
12
V1.3, 2010-04