ICSSSTUAF32866B Datasheet, PDF (9/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Logic Diagram (1:2)
COMMERCIAL TEMPERATURE GRADE
G2
RESET
CLK ^H1
J1
CLK
D2 - D3,
D5 - D6,
11
D8 - D14
A3, T3
VREF
C1 ^G5
PAR_IN ^G1
LPS0
(Internal Node)
D ^CCEE
CLK
R
Q
D2 - D3,
11 ^{D5 - D6,}
D8 - D14
Parity
Check
D2 - D3,
D5 - D6,
11 ^{D8 - D14}
0
DQ
1
CLK
R
D
Q
CLK
R
CE
1
D Q0
CLK
R
Q2A - Q3A,
11 _{Q5A - Q6A,}
Q8A - Q14A
11 _{Q2B - Q3B,}
Q5B - Q6B,
Q8B - Q14B
A2 _PPO
D2 _QERR
G6
C0
CLK
2-Bit
Counter
R
LPS1
(Internal Node)
0
D
Q
1
CLK
R
Parity Logic Diagram for 1:2 Register - A Configuration (Positive Logic);
C0 = 0, C1 = 1
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
9
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