ICSSSTUAF32866B Datasheet, PDF (15/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
VDD = 1.8V ± 0.1V
Symbol Parameter
Min.
Max. Units
fCLOCK Clock Frequency
410
MHz
tW
tACT1
tINACT2
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
1
ns
10
ns
15
ns
DCS before CLK↑, CLK↓, CSR HIGH; CSR before
CLK↑, CLK↓, DCS HIGH
0.6
tSU
Setup _{DCS before CLK↑, CLK↓, CSR LOW}
Time
0.5
ns
DODT, DOCKE, and data before CLK↑, CLK↓
0.5
PAR_IN before CLK↑, CLK↓
0.5
tH
Hold ^{DCS, DODT, DCKE, and data after CLK↑, CLK↓}
0.4
Time _{PAR_IN after CLK↑, CLK↓}
0.4
ns
1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
minimum time of tACT(max) after RESET is taken HIGH.
2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
time of tINACT(max) after RESET is taken LOW.
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
VDD = 1.8V ± 0.1V
Symbol Parameter
Min.
Max.
fMAX Max Input Clock Frequency
410
tPDM1 Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn
1.1
1.5
tPDQ2 Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn
0.4
0.8
tPDMSS1 Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn
1.6
tPD Propagation Delay, CLK and CLK to PPO
0.5
1.7
tLH LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to QERR
1.2
3
tHL HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to QERR
1
2.4
tPHL HIGH to LOW Propagation Delay, RESET↓ to PPO to Qn↓
3
tPLH LOW to HIGH Propagation Delay, RESET↓ to QERR↑
3
1 Design target as per JEDEC specifications.
2 Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
15
CONFIDENTIAL
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