ICSSSTUAF32866B Datasheet, PDF (23/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
RESET
DCS
COMMERCIAL TEMPERATURE GRADE
CSR
CLK
n
n +1
n+2
n+3
n+4
CLK
(1)
D1 - D14
Q1 - Q14
(1,2)
PARIN
PPO
(not used)
(3)
QERR
tACT
tSU
tH
tPDM, tPDMSS
CLK to Q
tSU
tH
tPD
CLK to PPO
tPHL
CLK to QERR
Data to QERR Latency
tPHL, tPLH
CLK to QERR
H, L, or X
H or L
Timing Diagram for the Second SSTUBF32866B (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1, RESET
Switches from L to H
NOTES:
1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of tactmax, to avoid false
error.
2.PAR_IN is driven from PPO of the first SSTUAF32866 device.
3.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
23
CONFIDENTIAL
IDT74SSTUBF32866B
7067/9