ICSSSTUAF32866B Datasheet, PDF (12/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Terminal Functions
Terminal Name
GND
VDD
VREF
ZOH
ZOL
CLK
CLK
C0, C1
RESET
CSR, DCS
D1 - D25
DODT
DCKE
Q1 - Q25
QCS
QODT
QCKE
PPO
PAR_IN
QERR
Electrical
Characteristics
Ground Input
1.8V nominal
0.9V nominal
Input
Input
Differential Input
Differential Input
LVCMOS Input
LVCMOS Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
SSTL_18 Input
Open Drain Output
Description
Ground
Power Supply Voltage
Input Reference Clock
Reserved for future use
Reserved for future use
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs
Asynchronous Reset Input. Resets registers and disables VREF
data and clock differential-input receivers.
Chip Select Inputs. Disables outputs D1 - D24 output switching
when both inputs are HIGH.
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
The outputs of this register bit will not be suspended by the DCS
and CSR controls
The outputs of this register bit will not be suspended by the DCS
and CSR controls
Data Outputs that are suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Partial Parity Output. Indicates off parity of D1 - D25
Parity Input arrives one cycle after corresponding data input
Output Error bit, generated one cycle after the corresponding data
output
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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