ICS9LRS3187B Datasheet, PDF (9/20 Pages) Integrated Device Technology – PROGRAMMABLE TIMING CONTROL HUB FOR INTEL BASED SYSTEMS

ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
Datasheet
Byte 9 Output Control Register
Bit Pin
Name
Description
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
Reserved
Reserved
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
1
IO_VOUT1
IO Output Voltage Select
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
Byte 10 Output Control Register
Bit Pin
Name
Description
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
CPU 1 Stop Enable Enables control of CPU1 with CPU_STOP#
0
CPU 0 Stop Enable Enables control of CPU 0 with CPU_STOP#
Byte 11 Reserved Register
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
CPU1_AMT_EN
1
PCI-E_GEN2
0
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
M1 mode clk enable
Determines if PCI-E Gen2 compliant
Reserved
Byte 12 Byte Count Register
Bit Pin
Name
7
Reserved
6
Reserved
5
BC5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Description
Read Back byte count register,
max bytes = 32
Type
RW
R
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
R
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
-
-
-
-
-
-
See Table 3: V_IO Selection
(Default is 0.8V)
Default
0
0
1
0
0
1
0
1
0
-
-
-
-
-
-
Free Running
Free Running
1
-
-
-
-
-
-
Stoppable
Stoppable
Default
0
0
0
0
0
0
1
1
0
-
Disable
non-Gen2
-
1
-
Enable
PCI-E Gen2
Compliant
-
Default
0
0
0
0
0
1
1
1
0
1
Default
0
0
0
0
1
1
0
1
IDT^® Programmable Timing Control Hub for Intel Based Systems
9
1602F—11/04/11