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ICS9LRS3187B Datasheet, PDF (13/20 Pages) Integrated Device Technology – PROGRAMMABLE TIMING CONTROL HUB FOR INTEL BASED SYSTEMS
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
Datasheet
Absolute Maximum Ratings - DC Parameters, Industrial Temperature Range
PARAMETER
Maximum Supply Voltage
Maximum Supply Voltage
Maximum Input Voltage
Minimum Input Voltage
Storage Temperature
SYMBOL
VDDxxx
VDDxxx_IO
VIH
VIL
Ts
CONDITIONS
Supply Voltage
Low-Voltage Differential I/O Supply
3.3V Tolerant Inputs
Any Input
-
MIN
TYP
GND - 0.5
-65
Input ESD protection
ESD prot
Human Body Model
2000
Notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 Operation under these conditions is neither implied, nor guaranteed.
2 Maximum VIH is not to exceed VDD
3 Human Body Model
MAX
4.6
3.8
4.6
150
UNITS
V
V
V
V
°C
V
Notes
1
1
1,2
1
1
1,3
Electrical Characteristics - Input/Supply/Common Output DC Parameters, Industrial Temperature Range
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Ambient Operating Temp
Supply Voltage, Core
Supply Voltage, I/O
Input High Voltage
Input Low Voltage
Low Threshold Input - High Voltage
Low Threshold Input - Low Voltage
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Tambind
VDDxxx
VDDxxx_IO
VIHSE
VILSE
VIH_FSC
VIL_FSC
IIN
IINRES
VOHSE
VOLSE
IDDOP3.3
IDDOPIO
IDDiAMT3.3
IDDiAMTIO
IDDPD3.3
IDDPDIO
Fi
Lpin
CIN
COUT
CINX
Industrial Range
Supply Voltage
Low-Voltage Differential I/O Supply
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%, Voltage for which FSC = '1'
3.3 V +/-5%
VIN = VDD , VIN = GND
Inputs with pull up or pull down resistors
VIN = VDD , VIN = GND
Single-ended outputs, IOH = -1mA
Single-ended outputs, IOL = 1 mA
Full Active, CL = Full load; Idd 3.3V
Full Active, CL = Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
-40
3.135
0.9975
2
VSS - 0.3
0.7
VSS - 0.3
-5
-200
2.4
3.3
1.05
2.4
0.4
92
18
48
6
3.2
0
14.318
5
1.5
4
5
4
Clk Stabilization
TSTAB From VDD Power-Up or de-assertion of PD to 1st clock
Tfall_SE
Trise_SE
TFALL
TRISE
Fall/rise time of all 3.3V control inputs from 20-80%
SMBus Voltage
VDD
2.7
Low-level Output Voltage
VOLSMB
@ IPULLUP
Current sinking at VOLSMB = 0.4 V
IPULLUP
SMB Data Pin
4
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
Maximum SMBus Operating Frequency
FSMBUS
Spread Spectrum Modulation Frequency
fSSMOD
Triangular Modulation
30
Notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1Signal is required to be monotonic in this region.
2 Input leakage current does not include inputs with pull-up or pull-down resistors
3 3.3V referenced inputs are: SCLK, SDATA, and CKPWRGD
4 Frequency Select pins which have tri-level input
5 If present, not all parts have this feature.
3.3
5
32.54
MAX UNITS
85
°C
3.465
V
3.465
V
VDD + 0.3 V
0.8
V
3.3
V
0.35
V
5
uA
Notes
5
3
3
4
2
200
uA
V
1
0.4
V
1
110
mA
25
mA
5
65
mA
15
mA
5
8
mA
0.05
mA
5
15
MHz
7
nH
5
pF
6
pF
6
pF
1.8
ms
10
ns
1
10
ns
1
5.5
V
0.4
V
mA
1000
ns
300
ns
100
kHz
33
kHz
IDT® Programmable Timing Control Hub for Intel Based Systems
13
1602F—11/04/11