ICS9LRS3187B Datasheet, PDF (1/20 Pages) Integrated Device Technology – PROGRAMMABLE TIMING CONTROL HUB FOR INTEL BASED SYSTEMS

Datasheet
PROGRAMMABLE TIMING CONTROL HUB FOR
INTEL BASED SYSTEMS
ICS9LRS3187B
Recommended Application:
CK505 version 1.1 clock, with fully integrated voltage regulators
and series resistors
Output Features:
• 2 - CPU differential low power push-pull pairs
• 1 - SRC differential low power push-pull pair
• 1 - SATA differential low power push-pull pair
• 1 - DOT differential low power push-pull pair
• 1 - REF, able to drive 3 loads, 14.318MHz
• 1 - 27MHz_SS/non_SS single-ended output pair
Features/Benefits:
• Supports spread spectrum modulation, 0 to -0.5%
down spread for CPU and SRC clocks
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Available in commercial (0 to +70°C) and industrial
(-40 to +85°C) temperature ranges
• Meets PCIe Gen2 specifications
Key Specifications:
• CPU outputs cycle-cycle jitter <85ps
• SRC outputs cycle-cycle jitter <125ps
• +/- 100ppm frequency accuracy on all clocks
Pin Configuration
32 31 30 29 28 27 26 25
VDDDOT96MHz_3.3 1
24 VDDCPU_3.3
GNDDOT96MHz 2
23 CPUT0_LPR
DOT96T_LPR 3
22 CPUC0_LPR
9LRS3187 DOT96C_LPR 4
VDD_27MHz 5
21 GNDCPU
20 CPUT1_LPR
27MHz_nonSS 6
19 CPUC1_LPR
27MHz_SS 7
18 VDDCPU_IO
GND27MHz 8
17 VDDSRC_3.3
9 10 11 12 13 14 15 16
** Internal Pull-Down Resistor
* Internal Pull-Up Resistor
32-pin MLF
IDT^® Programmable Timing Control Hub for Intel Based Systems
1
1602F—11/04/11