ICS9LPRS535 Datasheet, PDF (9/17 Pages) Integrated Device Technology – 48-pin CK505 for Intel Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
PCI_STOP# Power Management
SMBus OE Bit
Enable
Disable
PCI_STOP#
1
0
X
Single-ended Clocks
Stoppable
Running
Free running
Running
Low
Running
Low
Differential Clocks
(Except CPU)
Stoppable Free running
Running
Running
CK= High
CK# = Low
Running
CK= Pull down, CK# = Low
CPU_STOP# Power Management
SMBus OE Bit
Enable
CPU_STOP#
1
0
Disable
X
CPU Clocks
Stoppable Free running
Running
Running
CK= High
CK# = Low
Low
Running
CR# Power Management
SMBus OE Bit
CR#
Enable
1
0
Disable
X
Differential Clocks
(Except CPU)
CR# controlled Free running
Running
Running
CK= Pull down, CK# = Low
CK = Pull down, CK# = Low
PD# Power Management
Single-ended Clocks
(Except SE1)
Device State
w/o Latched input w/Latched input
Latches Open
SE1
w/B11b5 = 0
SE1
w/B11b5 = 1
Low
Power Down
Low
M1
Virtual Power Cycle
to Latches Open
25MHz
Hi-Z
Low
25MHz
25MHz
Differential Clocks
(Except CPU1)
CK= Pull down,
CK# = Low
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
CK= Pull down,
CK# = Low
CPU1
CK= Pull down,
CK# = Low
CK= Pull down
CK# = Low
Running
CK= Pull down,
CK# = Low
1461A—07/28/09
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