ICS9LPRS535 Datasheet, PDF (2/17 Pages) Integrated Device Technology – 48-pin CK505 for Intel Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
SSOP/TSSOP Pin Description
PIN #
PIN NAME
1 PCI0/CR#_A
2 VDDPCI
3 PCI4/SRC5_EN
4 PCI_F5/ITP_EN
5 GNDPCI
6 VDD48
7 USB_48MHz/FSLA
8 GND48
9 VDD96_IO
10 DOT96T_LPR/SRCT0_LPR
11 DOT96C_LPR/SRCC0_LPR
12 GND
TYPE
DESCRIPTION
3.3V PCI clock output or CR#_A input. Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in
I/O ^{Byte 2, bit 0.}
Byte 5, bit 7: 0 = PCI0 enabled (default), 1= CR#_A enabled.
Byte 5, bit 6: 0 = CR#_A controls SRC0 (default), 1= CR#_A# controls SRC2.
PWR Power supply for PCI clocks, nominal 3.3V
3.3V PCI clock output / SRC5 enable strap. On powerup, the logic value on this pin determines if SRC5 or
I/O ^{CPU_STOP#/PCI_STOP# is enabled. The latched value controls the pin function as follows}
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On
powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair.
I/O _{0 =SRC8/SRC8#}
1 = ITP/ITP#
PWR Ground pin for the PCI outputs
PWR Power pin for the 48MHz output.3.3V
I/O ^{3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed}
48MHz USB clock output. 3.3V.
PWR Ground pin for the 48MHz outputs
PWR Power pin for the DOT96 clocks, nominal 1.05V to 3.3V.
True clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRCT0. After
OUT ^{powerup, this pin function may be changed to DOT96T via SMBus Byte 1, bit 7 as follows:}
0= SRC0T
1=DOT96T
Complementary clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is
OUT ^{SRC0C. After powerup, this pin function may be changed to DOT96C via SMBus Byte 1, bit 7 as follows:}
0= SRC0C
1=DOT96C
PWR Ground pin.
13 VDD
14 SE1
15 GND
16 SRCT2_LPR/SATAT_LPR
17 SRCC2_LPR/SATAC_LPR
18 GNDSRC
19 SRCT3_LPR/CR#_C
20 SRCC3_LPR/CR#_D
21 VDDSRC_IO
22 SRCT4_LPR
23 SRCC4_LPR
PWR Power supply, nominal 3.3V
OUT CK505 Singled Ended Output 1. 3.3V.
PWR Ground pin.
OUT
OUT
True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
Complementary clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor
to GND needed.
PWR Ground pin for the SRC outputs
True clock of push-pull SRC output with int. 33ohm series resistor/CR#_C input. Disable SRC3 via Byte 4, bit 7, before using as
I/O
CR#_C.
Byte 5, bit 3: 0=SRC3 (default), 1=CR#_C.
Byte 5, bit 2: 0=CR# C controls SRC0 (default), 1=CR# C controls SRC2
Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_D input. Disable SRC3 via Byte 4, bit 7,
I/O ^{before using as CR#_D.}
Byte 5, bit 1: 0=SRC3 (default),1=CR#_D.
Byte 5, bit 0: 0=CR#_D controls N/A (default), 1=CR#_D controls SRC4
PWR 1.05V to 3.3V from external power supply
OUT True clock of push-pull SRC output with int. 33ohm series resistor.
OUT Complementary clock of push-pull SRC output with int. 33ohm series resistor.
24 CPU_STOP#/SRCC5_LPR
I/O ^{Stops all CPUCLK, except those set to be free running clocks /}
Complementary clock of push-pull SRC pair with int. 33ohm series resistor.
1461A—07/28/09
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