ICS9LPRS535 Datasheet, PDF (7/17 Pages) Integrated Device Technology – 48-pin CK505 for Intel Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
Electrical Characteristics - USB48MHz
PARAMETER
SYMBOL
Long Accuracy
ppm
Clock period
T_period
Absolute min/max period
T_abs
CLK High Time
T_HIGH
CLK Low time
Output High Voltage
T_LOW
V_OH
Output Low Voltage
V_OL
Output High Current
I_OH
Output Low Current
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter, Cycle to cycle
I_OL
t_SLR
t_FLR
d_t1
t_jcyc-cyc
CONDITIONS
see Tperiod min-max values
48.00MHz output nominal
48.00MHz output nominal
I_OH = -1 mA
I_OL = 1 mA
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
V_T = 1.5 V
V_T = 1.5 V
MIN
-100
20.83125
20.48125
8.216563
7.816563
2.4
-29
29
1
1
45
MAX
100
20.83542
21.18542
11.15198
10.95198
0.55
-23
27
2
2
55
350
UNITS NOTES
ppm 2,4
ns 2,3
ns
2
V
V
V
V
mA
mA
mA
mA
V/ns 1
V/ns 1
%
2
ps
2
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
Clock period
Tperiod
14.318MHz output nominal
69.82033 69.86224 ns
Absolute min/max period
Tabs
14.318MHz output nominal
69.83400 70.84800 ns
CLK High Time
THIGH
29.97543 38.46654 V
CLK Low time
TLOW
29.57543 38.26654 V
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
-33
-33
mA
Output Low Current
IOL
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
30
38
mA
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
Duty Cycle
dt1
VT = 1.5 V
45
55
%
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
1000
ps
NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{Edge rate in system is measured from 0.8V to 2.0V.}
2 _{Duty cycle, Peroid and Jitter are measured with respect to 1.5V}
3 _{The average period over any 1us period of time}
4 _{Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz}
Notes
2, 4
2, 3
2
1
1
2
2
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER
CPU Jitter - Cycle to Cycle
SRC Jitter - Cycle to Cycle
DOT Jitter - Cycle to Cycle
SYMBOL
CPUJC2C
SRCJC2C
DOTJC2C
CONDITIONS
Differential Measurement
Differential Measurement
Differential Measurement
MIN
MAX UNITS NOTES
85
ps
1
125
ps
1,2
250
ps
1
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system}
performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece
2 _{Phase jitter requirement: The deisgnated Ge2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a}
componnet test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement
methodology is as defined by the PCI SIG.
1461A—07/28/09
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