ICS9LP525-2 Datasheet, PDF (9/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Desktop Systems

ICS9LP525-2
PC MAIN CLOCK
E lectrical C haracteristics - P C IC LK /P C IC LK _F
PARAMETER
Long A ccuracy
Clock period
A bsolute m in/m ax period
Rising Edge Slew Rate
Falling Edge Slew Rate
Pin to Pin Skew
Intential PCI to PCI delay
Duty Cycle
Jitter, Cycle to cycle
SYMBOL
ppm
T _period
T_abs
t_SLR
t _{FL R}
t_skew
t_skew
d_t1
t _{jc y c -c y c}
CONDITIONS
see Tperiod m in-m ax values
33.33M Hz output no spread
33.33M Hz output spread
33.33M Hz output no spread
33.33M Hz output nom inal/spread
M easured from 0.8 to 2.0 V
M easured from 2.0 to 0.8 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V
Intentional PCI Clock to Clock Delay
200 ps nominal steps
MIN
-100
29.99700
30.08421
29.49700
29.56617
1
1
100
45
MAX
100
30.00300
30.23459
30.50300
30.58421
4
4
250
200
55
500
UNITS
ppm
ns
ns
ns
ns
V/ns
V/ns
ps
ps
%
ps
NOTES
1,2
2
2
2
2
1
1
2
2
2
2
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
E lectrical C haracteristics - U S B 48MH z
PARAMETER
Long A ccuracy
Clock period
A bsolute m in/m ax period
CLK High Time
CLK Low time
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter, Cycle to cycle
SYMBOL
ppm
T _period
T_abs
T _{HI G H}
T_LOW
t_SLR
t _{FL R}
d_t1
t _{jc y c -c y c}
CONDITIONS
see Tperiod m in-m ax values
48.00MHz output nominal
48.00MHz output nominal
M easured from 0.8 to 2.0 V
M easured from 2.0 to 0.8 V
V_T = 1.5 V
V_T = 1.5 V
MIN
-100
20.83125
20.48125
8.216563
7.816563
1
1
45
MAX
100
20.83542
21.18542
11.15198
10.95198
2
2
55
350
UNITS
ppm
ns
ns
V
V
V/ns
V/ns
%
ps
NOTES
2,4
2,3
2
1
1
2
2
E lectrical C h aracteristics - R E F-14.318MH z
PARAMETER
Long A ccuracy
Clock period
A bsolute m in/m ax period
CLK High Time
CLK Low time
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter, Cycle to cy cle
SYMBOL
ppm
Tperiod
Tabs
THIGH
TLOW
tSLR
tFLR
dt1
tjc y c -c y c
CONDITIONS
s ee Tperiod m in-m ax v alues
14.318MHz output nom inal
14.318MHz output nom inal
M easured from 0.8 to 2.0 V
M easured from 2.0 to 0.8 V
VT = 1.5 V
VT = 1.5 V
MIN
-100
69.82033
69.83400
29.97543
29.57543
1
1
45
MAX
100
69.86224
70.84800
38.46654
38.26654
4
4
55
1000
UNITS
ppm
ns
ns
V
V
V/ns
V/ns
%
ps
Notes
2, 4
2, 3
2
1
1
2
2
NO TES on SE outputs: (unless otherw ise noted, guaranteed by design and ch aracterizatio n, not 100% tested in pro duction).
1_{Edge rate in s y s tem is meas ured from 0.8V to 2.0V.}
2 _{Duty c y c le, Peroid and J itter are meas ured w ith res pec t to 1.5V}
3 _{T he av erage period ov er any 1us period of time}
4 _{Us ing frequenc y c ounter with the meas urment interv al equal or greater that 0.15s , target frequenc ies are 14.318180 MHz , 33.333333MHz and 48.000000MHz}
IDT^TM/ICS^TM PC MAIN CLOCK
1397—11/08/10
9