ICS9LP525-2 Datasheet, PDF (6/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Desktop Systems

ICS9LP525-2
PC MAIN CLOCK
A bsolute Maxim um R atings - D C P aram eters
PARAMETER
SYMBOL
Maximum Supply Voltage
VDDxxx
Maximum Supply Voltage
VDDxxx_IO
Maximum Input Voltage
Minimum Input Voltage
Case Tem perature
V_IH
V_IL
Tcase
S torage Tem perature
Ts
Input E S D protection
E S D prot
1_{G uaranteed by des ign and c harac teriz ation, not 100% tes ted in produc tion.}
2 _{O peration under thes e c onditions is neither im plied, nor guaranteed.}
CONDITIONS
Supply Voltage
Low-V oltage Differential I/O S upply
3.3V Inputs
Any Input
-
Human Body Model
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
115
150
UNITS
V
V
V
V
°_C
°_C
V
Notes
7
7
4,5,7
4,7
4,7
6,7
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
Ambient Operating Temp
Supply Voltage
Supply Voltage
SYMBOL
Tambient
VDDxxx
VDDxxx_IO
CONDITIONS
-
Supply Voltage
Low-Voltage Differential I/O Supply
Input High Voltage
Input Low Voltage
Low Threshold Input-
High Voltage
Low Threshold Input-
FSC = '1' Voltage
Low Threshold Input-
FSA,FSB = '1' Voltage
Low Threshold Input-
Low Voltage
V_IHSE
V_ILSE
V_{IH_FS_TEST}
V_{IH_FS_FSC}
V_{IH_FS_FSAB}
V_{IL_FS}
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
V_{IL_CFGHI}
V_{IL_CFGMID}
V_{IL_CFGLO}
I_IN
I_INRES
V_OHSE
V_OLSE
I_DDOP3.3
I_DDOPIO
I_DDiAMT3.3
I_DDiAMTIO
I_DDPD3.3
I_DDPDIO
F_i
L_pin
C_IN
C_OUT
C_INX
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
V_IN = V_{DD ,} V_IN = GND
Inputs with pull up or pull down resistors
V_IN = V_{DD ,} V_IN = GND
Single-ended outputs, I_OH = -1mA
Single-ended outputs, I_OL = 1 mA
Full Active, C_L = Full load; Idd 3.3V
Full Active, C_L = Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
MIN
0
3.135
0.72
2
V_SS - 0.3
MAX
70
3.465
0.9
V_DD + 0.3
0.8
UNITS
°C
V
V
V
V
2 VDD + 0.3 V
Notes
10
3
3
8
0.7
1.5
V
8
0.7 VDD+0.3 V
V_SS - 0.3 0.35
V
2.4 VDD+0.3 V
9
1.3
2
V
9
V_SS - 0.3
0.9
-5
5
V
9
uA
2
-200
200
uA
2.4
V
1
0.4
V
1
200
mA
70
mA
10
80
mA
10
mA
5
mA
0.1
mA
10
15
MHz
7
nH
1.5
5
pF
6
pF
6
pF
Clk Stabilization
T_STAB
From VDD Power-Up or de-assertion of PD to 1st clock
1.8
ms
Tdrive_CR_off
Tdrive_CR_on
Tdrive_CPU
Tfall_SE
Trise_SE
SMBus Voltage
Low-level Output Voltage
Current sinking at
V_OLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
T_DRCROFF
Output stop after CR deasserted
T_DRCRON
T_DRSRC
Output run after CR asserted
CPU output enable after
PCI_STOP# de-assertion
T_FALL
T_RISE
Fall/rise time of all 3.3V control inputs from 20-80%
V_DD
2.7
V_OLSMB
@ I_PULLUP
400
ns
0
us
10
ns
10
ns
10
ns
5.5
V
0.4
V
I_PULLUP
SMB Data Pin
4
mA
T_RI2C
T_FI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
ns
300
ns
Maximum SMBus Operating Frequency F_SMBUS
100
kHz
Spread Spectrum Modulation
Frequency
IDT^TM/ICS^TM PC MAIN CLOCK
f_SSMOD
Triangular Modulation
30
33
kHz
1397—11/08/10
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