ICS9LP525-2 Datasheet, PDF (7/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Desktop Systems

ICS9LP525-2
PC MAIN CLOCK
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{Signal is required to be monotonic in this region.}
2 _{input leakage current does not include inputs with pull-up or pull-down resistors}
3 _{3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.}
4 _{Intentionally blank}
5 _{Maximum VIH is not to exceed VDD}
6 _{Human Body Model}
7 _{Operation under these conditions is neither implied, nor guaranteed.}
8 _{Frequency Select pins which have tri-level input}
9 _{PCI3/CFG0 is optional}
10 _{If present. Not all parts have this feature.}
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS NOTES
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
Differential Voltage Swing
Crossing Point Voltage
Crossing Point Variation
Maximum Output Voltage
Minimum Output Voltage
Duty Cycle
CPU Skew
CPU[1:0] Skew
CPU[2_ITP:0] Skew
SRC[10:0] Skew
tSLR
tFLR
tSLVAR
VSWING
VXABS
VXABSVAR
VHIGH
VLOW
DCYC
CPUSKEW
CPUSKEW10
CPUSKEW20
SRCSKEW
Averaging on
Averaging on
Averaging on
Averaging off
Averaging off
Averaging off
Averaging off
Averaging off
Averaging on
Averaging on
Differential Measurement
Differential Measurement
Differential Measurement
2.5
4
V/ns 2, 3
2.5
4
V/ns 2, 3
20
% 1, 10
300
mV
2
300
550
mV 1,4,5
140
mV 1,4,9
1150
mV
1,7
-300
mV
1,8
45
55
%
2
100
ps
100
ps
1
150
ps
1
3000
ps 1,6,11
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{Measurement taken for single ended waveform on a component test board (not in system)}
2 _{Measurement taken from differential waveform on a component test board. (not in system)}
3 _{Slew rate emastured through V_swing voltage range centered about differential zero}
4 _{Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)}
5 _{Only applies to the differential rising edge (Clock rising, Clock# falling)}
6 _{Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.}
7 _{The max voltage including overshoot.}
8 _{The min voltage including undershoot.}
9 _{The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced}
modulation by setting C_cross_delta to be smaller than V_Cross absolute.
10 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets}
Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
11 _{For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.}
C lock Jitter S pecs - Low P ower D ifferential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS NOTES
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential M easurem ent
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential M easurem ent
125
ps
1,2
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential M easurem ent
250
ps
1
NO TES on DIF O utput Jitter: (unless otherw ise noted, guaranteed by design and characterization, not 100% tested in production).
1_{J Itter s pec s are s pec ified as meas ured on a c loc k c harac teriz ation board. Sy s tem des igners need to tak e s pec ial c are not to us e thes e numbers , as the in-s y s tem performanc e w ill be}
s omew hat degraded. T he rec eiv er EMT S (c his pet or C PU ) w ill hav e the rec eiv er jitter s pec s as meas ured ina real s y s tem.
2 _{Phas e jitter requirement: T he deis gnated G e2 outputs w ill meet the referenc e c loc k jitter requiremernts from the PC I Ex pres s G en2 Bas e Spec . T he tes t is performed on a c omponnet}
tes t board under quiet c ondittions w ith all outputs on. J itter analy s is is performed us ing the s tandardiz ed tool prov ided by the PC I SIG .
IDT^TM/ICS^TM PC MAIN CLOCK
7
1397—11/08/10