ICS9DB102_10 Datasheet, PDF (9/13 Pages) Integrated Device Technology – Two Output Differential Buffer for PCIe Gen1 & Gen2

ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)
Byte 0
Pin #
Name
Control Function Type
0
1
Bit 7
-
SW_EN
Functions
Functions
Enables SMBus
Control
RW
controlled by
SMBus
registers
controlled by
device pins
Bit 6
-
RESERVED
RW
-
Bit 5
-
RESERVED
RW
-
Bit 4
-
RESERVED
RW
-
Bit 3
-
RESERVED
RW
-
Bit 2
-
RESERVED
RW
-
Bit 1
-
PLL BW #adjust
Selects PLL
Bandwidth
RW
Low BW
High BW
Bit 0
-
PLL Enable
Bypasses PLL for
board test
RW
PLL bypassed
(fan out mode)
PLL enabled
(ZDB mode)
PWD
1
X
X
X
X
X
1
1
SMBus Table: Output Enable Register
Byte 1
Pin #
Name
Control Function Type
Bit 7
-
RESERVED
RW
Bit 6
-
RESERVED
RW
Bit 5
-
RESERVED
RW
Bit 4
-
RESERVED
RW
Bit 3
-
RESERVED
RW
Bit 2
-
RESERVED
RW
Bit 1
-
RESERVED
RW
Bit 0
-
RESERVED
RW
0
1
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
SMBus Table: Function Select Register
Byte 2
Pin #
Name
Control Function Type
Bit 7
RESERVED
RW
Bit 6
RESERVED
RW
Bit 5
-
RESERVED
RW
Bit 4
-
RESERVED
RW
Bit 3
-
RESERVED
RW
Bit 2
-
RESERVED
RW
Bit 1
-
RESERVED
RW
Bit 0
-
RESERVED
RW
SMBus Table: Vendor & Revision ID Register
Byte 3
Pin #
Name
Control Function Type
Bit 7
-
RID3
R
Bit 6
-
Bit 5
-
RID2
RID1
REVISION ID
R
R
Bit 4
-
RID0
R
Bit 3
-
VID3
R
Bit 2
-
Bit 1
-
VID2
VID1
VENDOR ID
R
R
Bit 0
-
VID0
R
0
1
-
-
-
-
-
-
-
-
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
PWD
0
0
0
1
0
0
0
1
IDT^® Two Output Differential Buffer for PCIe Gen1 & Gen2
9
852 REV K 04/01/10