ICS9DB102_10 Datasheet, PDF (4/13 Pages) Integrated Device Technology – Two Output Differential Buffer for PCIe Gen1 & Gen2

ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
T_A = Tambient; V_DD = 3.3 V +/-5%; C_L =2pF, R_S=33.2^Ω, R_P=49.9^Ω, I_REF = 475^Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo
V_O = V_x
3000
Voltage High
VHigh
Statistical measurement on
660
Voltage Low
VLow
single ended signal using
-150
Max Voltage
Vovs
Measurement on single ended
Min Voltage
Vuds
signal using absolute value. -300
TYP
MAX
850
150
1150
UNITS NOTES
Ω
1
mV
1,3
1,3
mV
1,3
1,3
Crossing Voltage (abs) Vcross(abs)
250 350 550
mV
1,3
Crossing Voltage (var) d-Vcross
Variation of crossing over all
edges
12
140
mV
1,3
Long Accuracy
ppm
see Tperiod min-max values
0
ppm 1,2
Average period
Tperiod
100.00MHz nominal
100.00MHz spread
9.9970
9.9970
10.0030 ns
2
10.0533 ns
2
Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720
ns
1,2
Rise Time
t_r
V_OL = 0.175V, V_OH = 0.525V
175
700
ps
1
Fall Time
t_f
V_OH = 0.525V V_OL = 0.175V
175
700
ps
1
Rise Time Variation
d-t_r
30
125
ps
1
Fall Time Variation
d-t_f
30
125
ps
1
Input to Output Delay
Duty Cycle
t_pd
t_pdbyp
d_t3
PLL Mode.
0
Bypass mode
3.7
Measurement from differential
45
wavefrom
150
ps
1
4.2
ns
1
55
%
1
Output-to-Output Skew
t_sk3
V_T = 50%
25
ps
1
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode. Measurement from
differential wavefrom
35
ps
1
t_jcyc-cycbyp Additve Jitter in Bypass Mode
1_{Guaranteed by design, not 100% tested in production.}
30
ps
1
.
2 _{The 9DB102 does not add a ppm error to the input clock}
3_{IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.}
IDT^® Two Output Differential Buffer for PCIe Gen1 & Gen2
4
852 REV K 04/01/10