ICS9DB102_10 Datasheet, PDF (5/13 Pages) Integrated Device Technology – Two Output Differential Buffer for PCIe Gen1 & Gen2

ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Electrical Characteristics - PLL Parameters
T_A = Tambient; Supply Voltage V_DD = 3.3 V +/-5%
Group
Parameter
Description
PLL Jitter Peaking j_peak-hibw
(PLL_BW = 1)
Min Typ Max Units Notes
0
1 2.5 dB
1,4
PLL Jitter Peaking j_peak-lobw
(PLL_BW = 0)
0
1
2
dB
1,4
PLL Bandwidth
pll_HIBW
(PLL_BW = 1)
PLL Bandwidth
pll_LOBW
(PLL_BW = 0)
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
Jitter, Phase
t_jphasePLL
(PLL_BW=1)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
2 2.5 3 MHz
0.4 0.5 1 MHz
40 108 ps
1,5
1,5
1,2,3
2.7 3.1 ps rms 1,2,3
2.2 3.1 ps rms 1,2,3
1.3 3 ps rms 1,2,3
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
IDT^® Two Output Differential Buffer for PCIe Gen1 & Gen2
5
852 REV K 04/01/10