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| ICS87001I-01 Datasheet, PDF (9/14 Pages) Integrated Device Technology – Maximum output frequency | |||
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ICS87001I-01 Data Sheet
Parameter Measurement Information, continued
LVCMOS/LVTTL CLOCK DIVIDER
CLK0, CLK1
Q
VDD
2
VDDO
2
t
PD
Propagation Delay
20%
Q
80%
tR
Output Rise/Fall Time
80%
tF
20%
V
DDO
Q
2
t PW
t
PERIOD
odc = t PW x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
OE
(High-level
enabling)
VDD/2
VDD/2
VDD
0V
tEN
Output Q
tDIS
VDDO/2
Output Enable/Disable Time
VOH
VDDO/2
Applications Information
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kï
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kï resistor can be used.
ICS87001BGI-01 REVISION A JANUARY 23, 2013
9
©2013 Integrated Device Technology, Inc.
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