ICS87001I-01 Datasheet, PDF (1/14 Pages) Integrated Device Technology – Maximum output frequency

LVCMOS/LVTTL Clock Divider
ICS87001I-01
DATA SHEET
General Description
The ICS87001I-01 is a low skew, ÷1, ÷2, ÷3, ÷4, ÷5, ÷6, ÷8, ÷16
LVCMOS/LVTTL Clock Divider. The ICS87001I-01 has selectable
clock inputs that accept single ended input levels. Output enable pin
controls whether the output is in the active or high impedance state.
The ICS87001I-01 is characterized at 3.3V, 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed part-to-part skew characteristics make the
ICS87001I-01 ideal for those applications demanding well defined
performance and repeatability.
Features
• One LVCMOS / LVTTL output
• Selectable LVCMOS / LVTTL clock inputs
• Maximum output frequency: 250MHz
• Part-to-part skew: 135ps (typical)
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK_SEL ^Pulldown
N Output Divider
N2:N0
CLK0
Pulldown ₀
0 0 0 ÷1 (default)
0 0 1 ÷2
0 1 0 ÷3
Q
0 1 1 ÷4
CLK1
Pulldown ₁
1 0 0 ÷5
1 0 1 ÷6
1 1 0 ÷8
1 1 1 ÷16
3
N2:N0 ^Pulldown
OE ^Pullup
Pin Assignment
OE 1
VDD 2
CLK0 ₃
CLK_SEL 4
CLK1 5
N2 6
N1 7
N0 8
16 VDDO
15 _nc
14 _Q
13 _nc
12 _GND
11 _nc
10 _nc
9 _GND
ICS87001I-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
ICS87001BGI-01 REVISION A JANUARY 23, 2013
1
©2013 Integrated Device Technology, Inc.