ICS87001I-01 Datasheet, PDF (2/14 Pages) Integrated Device Technology – Maximum output frequency

ICS87001I-01 Data Sheet
LVCMOS/LVTTL CLOCK DIVIDER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
OE
Input
Pullup
Output enable. When LOW, output is in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
2
V_DD
Power
3, 5
CLK0, CLK1
Input
Pulldown
Power supply pin.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
4
CLK_SEL
Input
Pulldown
Input clock selection. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
6, 7, 8
N2, N1, N0
Input
Pulldown Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3.
9, 12
GND
Power
Power supply ground.
10, 11, 13, 15
nc
Unused
No connect.
14
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
16
V_DDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
C_PD
Power Dissipation
Capacitance
R_OUT
Output Impedance
Test Conditions
V_DDO = 3.465V
V_DDO = 2.625V
V_DDO = 1.95V
V_DDO = 3.3V±5%
V_DDO = 2.5V±5%
V_DDO = 1.8V±0.15V
Minimum
Typical
4
51
51
6
5
5
17
20
28
Maximum
Units
pF
k
k
pF
pF
pF



Function Table
Table 3. Programmable Output Divider Function Table
Inputs
N2
N1
N0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
N Divider Value
÷1 (default)
÷2
÷3
÷4
÷5
÷6
÷8
÷16
ICS87001BGI-01 REVISION A JANUARY 23, 2013
2
Maximum Output Frequency (MHz)
250
125
83.333
62.5
50
41.667
31.25
15.625
©2013 Integrated Device Technology, Inc.