ICS854S013 Datasheet, PDF (9/14 Pages) Integrated Device Technology – LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER

ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 2A to 2F show interface examples for the
HiPerClockS PCLK/nPCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
PCLK
R1
100
nPCLK
HiPerClockS
PCLK/nPCLK
Figure 2A. HiPerClockS PCLK/nPCLK Input
Driven by an Open Collector CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
PCLK
nPCLK
HiPerClockS
R1
R2
84
84
Input
Figure 2B. HiPerClockS PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Figure 2C. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
3.3V
Zo = 50Ω
LVDS
R5
100
Zo = 50Ω
3.3V
3.3V
R3
R4
1k
1k
C1
PCLK
C2
nPCLK
HiPerClockS
R1
R2
1k
1k
PCLK/nPCLK
Figure 2E. HiPerClockS PCLK/nPCLK Input
Driven by an SSTL Driver
Figure 2F. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVDS Driver
IDT™ / ICS™ LVDS FANOUT BUFFER
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ICS854S013BG REV. A FEBRUARY 26, 2008