ICS854S013 Datasheet, PDF (12/14 Pages) Integrated Device Technology – LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER

ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Reliability Information
Table 7. θ_JA vs. Air Flow Table for a 20 Lead TSSOP
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
87.2°C/W
Transistor Count
The transistor count for ICS854S013 is: 363
1
82.9°C/W
PRELIMINARY
2.5
80.7°C/W
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8 Package Dimensions
All Dimensions in Millimeters
Symbol Minimum Maximum
N
20
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVDS FANOUT BUFFER
12
ICS854S013BG REV. A FEBRUARY 26, 2008