ICS854S013 Datasheet, PDF (4/14 Pages) Integrated Device Technology – LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER

ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Table 4C. LVDS DC Characteristics, V_DD = 3.3V ± 5%, T_A = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
V_OD
∆V_OD
V_OS
∆V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
Typical
360
50
1.35
50
Maximum
Units
mV
mV
V
mV
Table 5. AC Characteristics, V_DD = 3.3V ± 5%, T_A = 0°C to 70°C
Parameter Symbol
Test Conditions
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
tsk(b)
Bank Skew; NOTE 3, 4
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Minimum
Typical
TBD
<25
<50
0.15
200
50
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
>3
Units
GHz
ps
ps
ps
ps
%
IDT™ / ICS™ LVDS FANOUT BUFFER
4
ICS854S013BG REV. A FEBRUARY 26, 2008