ICS853S013I Datasheet, PDF (9/16 Pages) Integrated Device Technology – Output frequency

ICS853S013I Data Sheet
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figures 2A to 2F show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2A. PCLK/nPCLK Input
Driven by an Open Collector CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84Ω
84Ω
Input
3.3V
Zo = 50Ω
CML Built-In Pullup
Zo = 50Ω
R1
100Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2B. PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2C. PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. PCLK/nPCLKInput Driven by
a 3.3V LVPECL Driver with AC Couple
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
120Ω
R4
120Ω
3.3V
PCLK
R1
120Ω
R2
120Ω
nPCLK
LVPECL
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 2E. PCLK/nPCLK Input
Driven by an SSTL Driver
Figure 2F. PCLK/nPCLK Input
Driven by a 3.3V LVDS Driver
ICS853S013AMI REVISION A AUGUST 20, 2010
9
©2010 Integrated Device Technology, Inc.