ICS853S013I Datasheet, PDF (10/16 Pages) Integrated Device Technology – Output frequency

ICS853S013I Data Sheet
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Recommendations for Unused Output Pins
Inputs:
PCLKx/nPCLKx Inputs
For applications not requiring the use of a differential input, both the
PCLKx and nPCLKx pins can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from PCLKx
to ground. For applications
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Z_o = 50Ω
3.3V
+
LVPECL
Z_o = 50Ω
R1
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
* Z_o
_
Input
R2
50Ω
V_CC - 2V
RTT
Figure 3A. 3.3V LVPECL Output Termination
3.3V
LVPECL
3.3V
R3
R4
125Ω
125Ω
3.3V
Z_o = 50Ω
+
Z_o = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 3B. 3.3V LVPECL Output Termination
ICS853S013AMI REVISION A AUGUST 20, 2010
10
©2010 Integrated Device Technology, Inc.