844441 Datasheet, PDF (9/15 Pages) Integrated Device Technology – FemtoClock SAS/ SATA Clock Generator

844441 Datasheet
Schematic Example
Figures 3A and 3B are example 844441 application schematics for
either the 8 pin M package or the 16 pin G package. The schematic
examples focus on functional connections and are not configuration
specific. Refer to the pin description and functional tables in the
datasheet to ensure that the logic control inputs are properly set.
In this example, the device is operated at V_DD = 2.5V. A 12pF parallel
resonant 25MHz crystal is used with tuning capacitors C1 = C2
=14pF, which are recommended for frequency accuracy. Depending
on the variation of the parasitic stray capacity of the printed circuit
board traces between the crystal and the Xtal_In and Xtal_Out pins,
the values of C1 and C2 might require a slight adjustment to optimize
the frequency accuracy. Crystals with other load capacitance
specifications can be used, but this will require adjusting C1 and C2.
In circuit board design, return the capacitors to ground through a
single point contact close to the package. Two examples of
terminations for LVDS receivers without built-in termination are
shown in this schematic.
In order to achieve the best possible filtering, it is recommended that
the placement of the power filter components be on the device side
of the PCB as close to the power pins as possible. If space is limited,
the 0.1µF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
,'7^F^O^X⁶⁰³&^-U²\⁵V^-1W⁷D³O^crystal
R20 0
XTA L_OU T
4
1
2
C1
14pF
2 5MH z( 12p f)
X1
3 _{XT AL_ IN}
S SC _S EL0
S SC _S EL1
C2
14pF
U1
1
2 ^{XTA L_OU T}
3 ^{XTA L_I N}
4 ^{SS C _SE L0}
SS C _SE L1
8
G ND ₇
nQ ₆
Q5
VDD
C3
0.1uF
2.5V
F B1
1
2
VD D
Zo = 50 O hm
nQ
R1
+
Q
100
Zo = 50 O hm
-
Pl ace th e 0.1 uF by pas s c ap
di rec tly a dja cen t to the V DD pin .
B LM18 BB 221S N 1
C5
0.1u F
C6
10uF
Z o = 50 O hm
Q
Logic Input Pin Examples
Set Logic
Set Logic
V DD _{Input to '1'} V DD _{Input to '0'}
RU 1
1K
To Logic
Input
pi ns
RD 1
N ot I ns t all
RU2
N ot I ns t all
To Logic
Input
pins
RD2
1K
R3
50
+
C9
0.1u F
-
R4
50
Z o = 50 O hm
nQ
Alternate LVDS Termination
Figure 3A. 844441 Schematic Example
©2016 Integrated Device Technology, Inc.
9
Revison E, November 2, 2016