844441 Datasheet, PDF (11/15 Pages) Integrated Device Technology – FemtoClock SAS/ SATA Clock Generator

844441 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 844441.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 844441 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for V_DD = 2.5V + 5% = 2.625V, which gives worst case results.
Total Power _MAX = V_{DD_MAX} * I_{DD_MAX} = 2.625V * 73mA = 191.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 96°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.192W * 96°C/W = 103.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the supply voltage, air flow and the type of board (multi-layer).
Table 6A. Thermal Resistance _JA for 16 Lead TSSOP, Forced Convection
_JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
81.2°C/W
1
73.9°C/W
2.5
70.2°C/W
Table 6B. Thermal Resistance _JA for 8 Lead SOIC, Forced Convection
_JA vs. Air Flow
Linear Feet per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
96°C/W
200
87°C/W
500
82°C/W
©2016 Integrated Device Technology, Inc.
11
Revison E, November 2, 2016